1. Field of the Invention
The present invention relates to the fabrication of integrated circuits. More particularly, the invention relates to a process and apparatus for depositing dielectric layers on a semiconductor substrate.
2. Background of the Invention
One of the primary steps in the fabrication of modern semiconductor devices is the formation of metal and dielectric films on a semiconductor substrate by chemical reaction of gases. Such deposition processes are referred to as chemical vapor deposition or CVD. Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. The high temperatures at which some thermal CVD processes operate can damage device structures having layers previously formed on the substrate. A preferred method of depositing metal and dielectric films at relatively low temperatures is plasma-enhanced CVD (PECVD) techniques such as described in U.S. Pat. No. 5,362,526, entitled "Plasma-Enhanced CVD Process Using TEOS for Depositing Silicon Oxide", which is incorporated by reference herein. Plasma-enhanced CVD techniques promote excitation and/or disassociation of the reactant gases by the application of radio frequency (RF) energy to a reaction zone near the substrate surface, thereby creating a plasma of highly reactive species. The high reactivity of the released species reduces the energy required for a chemical reaction to take place, and thus lowers the required temperature for such PECVD processes.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore's Law), which means that the number of devices that will fit on a chip doubles every two years. Today's wafer fabrication plants are routinely producing devices having 0.35 .mu.m and even 0.18 .mu.m feature sizes, and tomorrow's plants soon will be producing devices having even smaller geometries.
In order to further reduce the size of semiconductor devices on integrated circuits, it has become necessary to use conductive materials having low resistivity and insulators having low k (dielectric constant &lt;4.0) to reduce the capacitive coupling between adjacent metal lines. Low k dielectric materials are generally porous and liner/barrier layers are used between the conductive materials and the insulators to prevent diffusion of byproducts such as moisture onto the conductive material as described in International Publication Number WO 94/01885. For example, moisture generated during formation of the low k insulator readily diffuses to the surface of the conductive metal and increases the resistivity of the conductive metal surface. A barrier/liner layer formed from conventional silicon oxide materials can block the diffusion of the byproducts. However, the barrier/liner layers typically have dielectric constants that are significantly greater than 4.0, and the high dielectric constants result in a combined insulator that does not significantly reduce the dielectric constant.
FIG. 1A illustrates a PECVD process for depositing a barrier/liner layer as described in International Publication Number WO 94/01885. The PECVD process deposits a multi-component dielectric layer wherein a silicon dioxide (SiO.sub.2) liner layer 2 is first deposited on a patterned metal layer having metal lines 3 formed on a substrate 4. The liner layer 2 is deposited by reaction of silane (SiH.sub.4) and nitrous oxide (N.sub.2 O). A self-planarizing low k dielectric layer 5 is then deposited on the liner layer 2 by reaction of a silane compound and a peroxide compound. The self-planarizing layer 5 retains moisture that is removed by annealing. The liner layer 2 is an oxidized silane film that has effective barrier properties when deposited in a manner which provides a dielectric constant of at least 4.5. The dielectric constant of the oxidized silane film can be decreased to about 4.1 by altering process conditions in a manner that decreases moisture barrier properties of the film. Conventional liner layers, such as SiN, have even higher dielectric constants, and the combination of low k dielectric layers with high k dielectric liner layers provides little or no improvement in the overall stack dielectric constant and capacitive coupling.
As shown in FIG. 1B, WO 94/01885 further describes an optional SiO.sub.2 cap layer 6 that is deposited on the low k dielectric layer 5 by the reaction of silane and N.sub.2 O. The cap layer 6 is also an oxidized silane film that has good barrier properties when deposited in a manner which provides a dielectric constant of about 4.5. Both the liner layer 2 and the cap layer 6 have a dielectric constant greater than 4.5 and the high dielectric constant layers substantially detract from the benefit of the low k dielectric layer 5.
U.S. Pat. No. 5,554,570 describes barrier layers for use with thermal CVD silicon oxides wherein an organosilane having a C-H group is oxidized instead of silane to increase the density of deposited films and to improve adhesion between the layers. For example, a thermal CVD layer produced from tetraethoxysilane (TEOS) and ozone, may be deposited between PECVD silicon oxide films produced from an organosilane and N.sub.2 O or O.sub.2.
The barrier layers described in the '570 patent are preferably dense silicon oxide layers having low carbon contents. The dense layers are deposited using 400 W of high frequency RF power although the use of low frequency RF power is asserted to improve film stress. The barrier layers are preferably produced from alkoxy silanes or chlorinated alkyl silanes and N.sub.2 O to reduce carbon content and increase the density of the layers
The '570 patent does not identify process conditions for making barrier layers having low dielectric constants and does not even suggest use of the barrier layers adjacent low k dielectric layers. There remains a need for dielectric layers having both low dielectric constants and good moisture barrier properties for use in sub-micron devices.
In addition to the limited utility for low k dielectric materials described above, many low k dielectric materials have low oxide content which makes the material inadequate as an etch stop layer. Silicon nitride has been the etch stop material of choice for making interconnect lines in low k dielectric materials. However, the silicon nitride has a relatively high dielectric constant (dielectric constant of about 7) compared to the surrounding low k dielectric layers. It has also been discovered that the silicon nitride may significantly increase the capacitive coupling between interconnect lines, even when an otherwise low k dielectric material is used as the primary insulator. This may lead to cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the device. There remains a need for low k dielectric layers which have sufficient oxide content for use as etch stop layers.
As devices get smaller, liner layers, cap layers, and etch stop layers contribute more to the overall dielectric constant of a multi-component dielectric layer. Ideally, a low k dielectric layer having both good barrier properties and sufficient oxide content for use as an etch stop could be identified and deposited in the same chambers as existing low k dielectric materials.